Implementation of a CPU Cache with the BipBip Tweakable Block Cipher
Advisor(s)
Firas Hassan
Confirmation
1
Document Type
Poster
Location
ONU McIntosh Center; Activities Room
Start Date
11-4-2025 12:00 PM
End Date
11-4-2025 12:50 PM
Abstract
This research presents a novel cache controller design leveraging the tweakable block cipher BipBip to enhance hardware security in consumer computers. BipBip, introduced in 2023, is a 24-bit tweakable block cipher with a 40-bit tweak optimized for low latency, achieving a 3-cycle encryption latency on modern ASIC implementations. The cache controller integrates BipBip into a direct-mapped cache architecture to encrypt all data written to and read from the cache, thereby mitigating hardware-level security vulnerabilities. Data encryption is performed via a pipelined 6-clock cycle BipBip encryptor with data-forwarding capabilities, while decryption leverages a 3-clock cycle BipBip decryptor for efficient data retrieval. Additionally, the controller employs a second BipBip decryptor to decrypt the 52-bit cache tags, utilizing a padded 64-bit input format to accommodate BipBip's cipher dimensions. The controller supports 128 cache sets, each storing 256-bit data blocks, divided into 64-bit words and 8-bit bytes, with address breakdown into a 52-bit tag, 7-bit set ID, 2-bit word ID, and 3-bit byte ID. By ensuring that all data within the CPU cache remains encrypted, this design addresses a significant security gap in consumer computing systems, where unauthorized hardware access can compromise sensitive information. The implementation highlights the feasibility of integrating BipBip's low-latency cryptographic properties into practical hardware applications, offering a robust step toward secure memory systems.
Keywords: cache encryption · tweakable block cipher · BipBip · hardware security
Recommended Citation
Hibler, Corbin; Hassan, Firas; and McKanna, Eric, "Implementation of a CPU Cache with the BipBip Tweakable Block Cipher" (2025). ONU Student Research Colloquium. 85.
https://digitalcommons.onu.edu/student_research_colloquium/2025/Posters/85
Open Access
Available to all.
Implementation of a CPU Cache with the BipBip Tweakable Block Cipher
ONU McIntosh Center; Activities Room
This research presents a novel cache controller design leveraging the tweakable block cipher BipBip to enhance hardware security in consumer computers. BipBip, introduced in 2023, is a 24-bit tweakable block cipher with a 40-bit tweak optimized for low latency, achieving a 3-cycle encryption latency on modern ASIC implementations. The cache controller integrates BipBip into a direct-mapped cache architecture to encrypt all data written to and read from the cache, thereby mitigating hardware-level security vulnerabilities. Data encryption is performed via a pipelined 6-clock cycle BipBip encryptor with data-forwarding capabilities, while decryption leverages a 3-clock cycle BipBip decryptor for efficient data retrieval. Additionally, the controller employs a second BipBip decryptor to decrypt the 52-bit cache tags, utilizing a padded 64-bit input format to accommodate BipBip's cipher dimensions. The controller supports 128 cache sets, each storing 256-bit data blocks, divided into 64-bit words and 8-bit bytes, with address breakdown into a 52-bit tag, 7-bit set ID, 2-bit word ID, and 3-bit byte ID. By ensuring that all data within the CPU cache remains encrypted, this design addresses a significant security gap in consumer computing systems, where unauthorized hardware access can compromise sensitive information. The implementation highlights the feasibility of integrating BipBip's low-latency cryptographic properties into practical hardware applications, offering a robust step toward secure memory systems.
Keywords: cache encryption · tweakable block cipher · BipBip · hardware security