Applying a Multi-Level Structure to High-Precision Priority Encoders
Advisor(s)
Dr. Firas Hassan
Dr. Ahmed Ammar
Confirmation
1
Document Type
Paper
Location
ONU McIntosh Center; Dean's Heritage Room
Start Date
8-4-2025 3:40 PM
End Date
8-4-2025 3:55 PM
Abstract
Priority encoders are a traditionally expensive hardware component, particularly at high input precisions (above 1024 bits). Due to this cost, they are often avoided, but could be leveraged to improve the performance of or provide an alternative method for various operations and algorithms, such as high-precision integer arithmetic. In this work, we introduce a generalized method for constructing high-precision priority encoders by dividing them into multiple levels. This builds upon our previous work which introduced the idea of the two-level priority encoder. We extend this concept to three levels using two different techniques (cascading and composition) and comment on further generalization. We analyze hardware delay and complexity as a function of input precision for both FPGA and ASIC implementation technologies, and compare the proposed implementation to existing methods. Our results show that the two-level priority encoder reduces complexity by about half, with a corresponding increase in delay. This highlights a key complexity-delay tradeoff. Additional levels introduce incremental improvements, but add overhead and have diminishing returns. Thus, each configuration is best for a particular range of input precisions, so we provide a set of implementation recommendations based on input precision and implementation technology.
Recommended Citation
Phillips, Maxwell; Hassan, Firas; and Ammar, Ahmed, "Applying a Multi-Level Structure to High-Precision Priority Encoders" (2025). ONU Student Research Colloquium. 25.
https://digitalcommons.onu.edu/student_research_colloquium/2025/Papers/25
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Applying a Multi-Level Structure to High-Precision Priority Encoders
ONU McIntosh Center; Dean's Heritage Room
Priority encoders are a traditionally expensive hardware component, particularly at high input precisions (above 1024 bits). Due to this cost, they are often avoided, but could be leveraged to improve the performance of or provide an alternative method for various operations and algorithms, such as high-precision integer arithmetic. In this work, we introduce a generalized method for constructing high-precision priority encoders by dividing them into multiple levels. This builds upon our previous work which introduced the idea of the two-level priority encoder. We extend this concept to three levels using two different techniques (cascading and composition) and comment on further generalization. We analyze hardware delay and complexity as a function of input precision for both FPGA and ASIC implementation technologies, and compare the proposed implementation to existing methods. Our results show that the two-level priority encoder reduces complexity by about half, with a corresponding increase in delay. This highlights a key complexity-delay tradeoff. Additional levels introduce incremental improvements, but add overhead and have diminishing returns. Thus, each configuration is best for a particular range of input precisions, so we provide a set of implementation recommendations based on input precision and implementation technology.