BipBip Cache Interface
Location
Ada, Ohio
Start Date
3-12-2024 12:00 AM
End Date
3-12-2024 12:00 AM
Description
This research presents a novel cache controller design leveraging the tweakable block cipher BipBip to enhance hardware security in consumer computers. BipBip, introduced in 2023 by Belkheyar et. al., is a 24-bit tweakable block cipher with a 40-bit tweak optimized for low latency, achieving a 3-cycle decryption latency. The cache controller integrates BipBip into a direct-mapped cache architecture to encrypt all data written to and read from the cache, thereby mitigating hardware-level security vulnerabilities. Data encryption is performed via a pipelined 6-clock cycle BipBip encryptor with data-forwarding capabilities, while decryption leverages a 3-clock cycle BipBip decryptor for efficient data retrieval. Additionally, the controller employs a second BipBip decryptor to decrypt the 52-bit cache tags, utilizing a padded 64-bit input format to accommodate BipBip's cipher dimensions. The controller supports 128 cache sets, each storing 256-bit data blocks, divided into 64-bit words and 8-bit bytes, with address breakdown into a 52-bit tag, 7-bit set ID, 2-bit word ID, and 3-bit byte ID. By ensuring that all data within the CPU cache remains encrypted, this design addresses a significant security gap in consumer computing systems, where unauthorized hardware access can compromise sensitive information. The implementation highlights the feasibility of integrating BipBip's low-latency cryptographic properties into practical hardware applications, offering a robust step toward secure memory systems. Keywords: cache encryption · tweakable block cipher · BipBip · hardware security.
Recommended Citation
Hibler, Corbin, "BipBip Cache Interface" (2024). College of Engineering Student Research Colloquium. 13.
https://digitalcommons.onu.edu/eng_student_research_colloquium/2024/Presentations/13
BipBip Cache Interface
Ada, Ohio
This research presents a novel cache controller design leveraging the tweakable block cipher BipBip to enhance hardware security in consumer computers. BipBip, introduced in 2023 by Belkheyar et. al., is a 24-bit tweakable block cipher with a 40-bit tweak optimized for low latency, achieving a 3-cycle decryption latency. The cache controller integrates BipBip into a direct-mapped cache architecture to encrypt all data written to and read from the cache, thereby mitigating hardware-level security vulnerabilities. Data encryption is performed via a pipelined 6-clock cycle BipBip encryptor with data-forwarding capabilities, while decryption leverages a 3-clock cycle BipBip decryptor for efficient data retrieval. Additionally, the controller employs a second BipBip decryptor to decrypt the 52-bit cache tags, utilizing a padded 64-bit input format to accommodate BipBip's cipher dimensions. The controller supports 128 cache sets, each storing 256-bit data blocks, divided into 64-bit words and 8-bit bytes, with address breakdown into a 52-bit tag, 7-bit set ID, 2-bit word ID, and 3-bit byte ID. By ensuring that all data within the CPU cache remains encrypted, this design addresses a significant security gap in consumer computing systems, where unauthorized hardware access can compromise sensitive information. The implementation highlights the feasibility of integrating BipBip's low-latency cryptographic properties into practical hardware applications, offering a robust step toward secure memory systems. Keywords: cache encryption · tweakable block cipher · BipBip · hardware security.