Priority Encoder-Based Algorithm for High-Precision Integer Multiplication

Advisor(s)

Dr. Firas Hassan

Dr. Ahmed Ammar

Confirmation

1

Document Type

Poster

Location

ONU McIntosh Center; McIntosh Activities Room

Start Date

21-4-2023 12:00 PM

End Date

21-4-2023 12:50 PM

Abstract

High-precision integer multiplication is critical for applications in physics, mathematics, digital signal processing, and most importantly, encryption. However, existing solutions must process every bit of the multiplier. This paper presents an improved method for shift-and-add multiplication leveraging a novel two-level structure for a priority encoder, decoder, and barrel shifter to optimize speed and hardware complexity, building upon our previous work in integer division. Each component splits a large input length into coarse and fine sections and processes each separately, significantly reducing complexity. The current algorithm takes sign and magnitude inputs, but could be integrated with a forthcoming work in high precision absolute value logic to allow streamlined processing of two's complement values. Furthermore, the FPGA implementation of the proposed algorithm uses multiple clocks to allow both rapid input of high-precision data over a serial connection and optimal multiplication speed. The proposed algorithm processes only the high bits of the multiplier. On average, this doubles performance compared to the traditional shift-and-add algorithm. The proposed algorithm outperforms existing methods in the best case and performs equally well in the worst case.

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Apr 21st, 12:00 PM Apr 21st, 12:50 PM

Priority Encoder-Based Algorithm for High-Precision Integer Multiplication

ONU McIntosh Center; McIntosh Activities Room

High-precision integer multiplication is critical for applications in physics, mathematics, digital signal processing, and most importantly, encryption. However, existing solutions must process every bit of the multiplier. This paper presents an improved method for shift-and-add multiplication leveraging a novel two-level structure for a priority encoder, decoder, and barrel shifter to optimize speed and hardware complexity, building upon our previous work in integer division. Each component splits a large input length into coarse and fine sections and processes each separately, significantly reducing complexity. The current algorithm takes sign and magnitude inputs, but could be integrated with a forthcoming work in high precision absolute value logic to allow streamlined processing of two's complement values. Furthermore, the FPGA implementation of the proposed algorithm uses multiple clocks to allow both rapid input of high-precision data over a serial connection and optimal multiplication speed. The proposed algorithm processes only the high bits of the multiplier. On average, this doubles performance compared to the traditional shift-and-add algorithm. The proposed algorithm outperforms existing methods in the best case and performs equally well in the worst case.