Implementation of a CPU Cache with the BipBip Tweakable Block Cipher
Location
Ada, Ohio
Start Date
9-12-2025 12:30 PM
End Date
9-12-2025 12:40 PM
Description
This work presents a hardware-adapted version of BipBip, a lightweight tweakable block cipher originally designed to decrypt 64-bit encrypted machine instructions with ultra-low latency of three clock cycles. Our goal is to repurpose BipBip for secure on-chip memory by integrating it into a direct-mapped data cache that supports both load and store operations. Unlike instruction decryption, cache operation requires decrypting both the tag and the data on every load to verify cache hits while simultaneously producing plaintext for the processor. Store operations are even more challenging, as encryption must occur on the critical path. The original three-cycle latency of BipBip is insufficient for storing, because an additional three cycles are required to generate the tweak associated with the encrypted data block. We propose a microarchitectural optimization that overlaps tweak generation with tag decryption: while the cache decrypts the tag to determine hit/miss, the cipher hardware precomputes the tweak for the data block. Upon a hit, only three additional cycles are required to encrypt the updated data before storing it back into the cache and setting the dirty bit.
The design is tested on a direct-mapped cache with 128 blocks, each block containing four 64-bit words and a 52-bit encrypted tag. The system is implemented on an FPGA and evaluated using both simulation and a custom serial I/O protocol for reading and writing cache contents. Results demonstrate the feasibility of integrating a three-cycle tweakable cipher into a practical data-cache pipeline with only six total cycles of store latency, making this a promising direction for low-latency encrypted memory systems.
Recommended Citation
Hibler, Corbin and McKanna, Eric, "Implementation of a CPU Cache with the BipBip Tweakable Block Cipher" (2025). College of Engineering Student Research Colloquium. 3.
https://digitalcommons.onu.edu/eng_student_research_colloquium/2025/Presentations/3
Implementation of a CPU Cache with the BipBip Tweakable Block Cipher
Ada, Ohio
This work presents a hardware-adapted version of BipBip, a lightweight tweakable block cipher originally designed to decrypt 64-bit encrypted machine instructions with ultra-low latency of three clock cycles. Our goal is to repurpose BipBip for secure on-chip memory by integrating it into a direct-mapped data cache that supports both load and store operations. Unlike instruction decryption, cache operation requires decrypting both the tag and the data on every load to verify cache hits while simultaneously producing plaintext for the processor. Store operations are even more challenging, as encryption must occur on the critical path. The original three-cycle latency of BipBip is insufficient for storing, because an additional three cycles are required to generate the tweak associated with the encrypted data block. We propose a microarchitectural optimization that overlaps tweak generation with tag decryption: while the cache decrypts the tag to determine hit/miss, the cipher hardware precomputes the tweak for the data block. Upon a hit, only three additional cycles are required to encrypt the updated data before storing it back into the cache and setting the dirty bit.
The design is tested on a direct-mapped cache with 128 blocks, each block containing four 64-bit words and a 52-bit encrypted tag. The system is implemented on an FPGA and evaluated using both simulation and a custom serial I/O protocol for reading and writing cache contents. Results demonstrate the feasibility of integrating a three-cycle tweakable cipher into a practical data-cache pipeline with only six total cycles of store latency, making this a promising direction for low-latency encrypted memory systems.